(1) Field of the Invention
The invention relates to the fabrication of Semiconductor integrated circuit devices, and more particularly to a cost effective method for forming a passivation layer on the top surface of interconnecting metal lines such that damage and extrusion in the surface of the passivation layer and SOG delamination over the metal lines are eliminated.
(2) Description of Prior Art
Metal lines of the various layers of conducting lines in a semiconductor device are separated by insulating layers such as silicon oxide and oxygen-containing polymers that are deposited using Chemical Vapor Deposition (CVD) techniques. The insulating layers are deposited over patterned layers of interconnecting lines where electrical contact between successive layers of interconnecting lines is established with metal vias created for this purpose in the insulating layers. Electrical contact to the chip is typically established by means of bonding pads that form electrical interfaces with patterned levels of interconnecting metal lines. Signal lines and power/ground lines can be connected to the bonding pads. After the bonding pads have been created on the surfaces of the chip package, the bonding pads are passivated and electrically insulated by the deposition of a passivation layer over the surface of the bonding pads. Passivation layer can contain silicon oxide/silicon nitride (SiO2/Si3N4) deposited by CVD. The passivation layer is patterned and etched to create openings in the passivation layer for the bonding pads after which a second and relatively thick passivation layer is deposited that further insulates and protects the surface of the chips from moisture and other contaminants and from mechanical damage during the final assembling of the chips. The chips are diced and further assembled on a single or multiple chip carrier, electrical contacts are then further established to the chips via the chip bonding pads.
The trend in the semiconductor industry to create ever denser circuit packages has resulted in packaging many integrated circuit chips in one package and to provide electrical interconnects between the chips within the package. One frequently used method where multiple chips are mounted in one package is the creation of a multi chip module (MCM). This approach has led to the creation of a multilayer structure in the MCM where active chips form the module and the chips are interconnected with a pattern of conducting lines. The conducting lines typically contain doped polysilicon, refractory metal silicides and metal. Via holes are provided that interconnect different layers of conducting lines. Typical dimensions for the conducing lines are a width of 6 to 20 um and a height of 5 to 10 um, conducting lines tend to be narrow in width and thick in the vertical direction. Signal lines are created in such a way as to reduce electrical cross talk between adjacent lines which requires that the conducting lines intersect under a 90-degree angle. To achieve proper creation of the layers of conducting lines and to minimize electrical interference between lines of different layers while at the same time meeting requirements of inter-layer insulation and device reliability, the different layers of conducting line patterns must be created in planes that are essentially flat and have good planarity.
Various materials have found application in the creation of passivation layers. Passivation layer can contain silicon oxide/silicon nitride (SiO2/Si3N4) deposited by CVD, passivation layer can be a photosensitive polyimide or can comprise titanium nitride. Another material often used for passivation layer is phosphorous doped silicon dioxide that is typically deposited over a final layer of aluminum interconnect using a Low Temperature CVD process. In recent years, photosensitive polyimide has frequently been used for the creation of passivation layers. Conventional polyimides have a number of attractive characteristics for their application in a semiconductor device structure such as the ability to fill openings of high aspect ratio, a relatively low dielectric constant (about 3.2), a simple process required for the depositing of a layer of polyimide, the reduction of sharp features or steps in the underlying layer, high temperature tolerance of cured polyimide. Photosensitive polyimides have these same characteristics but can, in addition, be patterned like a photoresist mask and can, after patterning and etching, remain on the surface on which it has been deposited to serve as a passivation layer. Typically and to improve surface adhesion and tension reduction, a precursor layer is first deposited by, for example, conventional photoresist spin coating. The precursor is, after a low temperature pre-bake, exposed using, for example, a step and repeat projection aligner and Ultra Violet (UV) light as a light source. The portions of the precursor that have been exposed in this manner are cross linked thereby leaving unexposed regions (that are not cross linked) over the bonding pads. During subsequent development, the unexposed polyimide precursor layer (over the bonding pads) is dissolved thereby providing openings over the bonding pads. A final step of thermal curing leaves a permanent high quality passivation layer of polyimide over the substrate.
For 0.5 um. and sub-half micron technologies, the spacing of the top metal becomes small enough to cause the creation of microscopic openings (keyholes) within the surface of deposited layers of passivation layers of Plasma Enhanced Oxide (PEOXIDE) or Plasma Enhanced Silicon Nitride (PESi3Ni4). The subsequently deposited photo resist that defines a passivation pattern will flow into these keyholes resulting in decreased thickness of the photo resist layer in the areas of the keyholes. This may result in damage to the passivation film during etching of the photoresist. The removal of the photoresist is a wet and dry strip process; Act 690 and NMP are used during this process and will also accumulate in the keyhole. The final step of alloying the remaining passivation layer requires elevated temperatures. The (in the keyhole) accumulated photoresist combined with the remnants of Act 690 and NMP (in the keyhole) evaporate at these elevated temperatures causing a violent chemical reaction and the extrusion of the photoresist from the keyhole.
FIGS. 1 through 7 show Prior Art processes used for the deposition of passivation layers over metal layers with the creation of bond pad contact.
FIG. 1 shows a Prior Art pattern of the top layer 12 of metal for interconnecting lines and the top layer 14 of metal for the formation of a bond pad. The layers of metal are deposited on the surface of a substrate 10.
Conventional semiconductor device processing calls for the deposition of passivation layer over the entire top surface of the wafer. The passivation layer forms an insulating, protective layer that shields and protects the surface that it covers from mechanical and chemical damage during subsequent device assembly and packaging. The passivation layer must therefore have good adhesion to the underlying metal and any level of interlevel dielectric over which it is deposited, it must provide uniform step coverage so as not to hinder subsequent steps of planarization, it must be deposited in a uniform thickness, it must protest against mechanical damage such as surface scratch while it must also protect against moisture penetration, it must not introduce stress related problems while easy patterning of the passivation layer is required. It is clear that, in order to meet the requirements that are placed on the passivation layer; the passivation layer must be thick. In many applications, the passivation layer is therefore created using two depositions of passivation material.
FIG. 2 shows the deposition of a first passivation layer 16 of Plasma Enhanced oxide. This layer 16 is a blank deposition over the pattern 12 of the top layer metal for the interconnections and over the top layer metal 14 for the bond pad. The layer 16 of PE oxide typically is about 2000 Angstrom thick. Layer 16 reduces the mechanical stress and the hydrogen content of the overall passivation layer.
FIG. 3 shows the deposition of a second passivation layer 18 of Plasma Enhanced Si3Ni4 over the first passivation layer 16. This second passivation layer typically is about 7000 Angstrom thick. This nitride layer protects the underlying device against environmental impact such as mechanical scratch, mobile ion impurities such as sodium atoms and against high environmental humidity. Where the spacing between the pattern of interconnect lines 12 is very small, that is 0.5 um or sub-half micron, the spacing is narrow enough that keyholes 20 will be formed on the top surface of the deposited passivation layer 18. As keyholes are defined any surface irregularities that appear in the surface of the passivation layer. These irregularities, when observed in cross section, often have the profile of a keyhole and are therefore generally referred to as keyhole formations. Keyholes may, at times, not be directly apparent or visible on the surface of the passivation layer as open areas or pitting in the surface. Keyholes can also be hidden below the surface of the passivation layer and can demonstrate their existence by causing poor planarization of the surface of the passivation layer.
After the creation of the passivation layer, the passivation layer must now be patterned whereby the passivation layer stays in place over the regions of the interconnecting metal (for the reasons mentioned above) while openings are created for bonding pads. The bonding contact mask is used for this purpose.
FIG. 4 shows the next step in the definition and creation of a bonding pad. A layer 22 of photoresist is deposited over the passivation layer 18; this layer 22 of photoresist is patterned (24) for the bonding pad 14. During the deposition of the photoresist, the photoresist 22 will flow into the keyholes 20 and cause a thinning in area 27 of the photoresist where the keyhole exists.
The pattern 24 of photoresist is defined through exposure and develop. The removal of the photoresist exposes the areas of the planarization layers 16 and 18 that are above the bonding pad 16.
FIG. 5 shows after the passivation etch whereby the passivation layers 16 and 18 have been etched down to the bonding pad 14. A wet or dry etch can be used for the etching of the passivation layer. Typically, dry etch is recommended due to metal corrosion concerns. After the passivation etch has been completed, the remainder of the photoresist will be removed.
FIG. 6 shows a cross section after the photoresist has been removed. The keyhole 20 caused a thinning of the photoresist around the keyhole in area 27 (FIG. 5). The etching of the photoresist may therefore damage the underlying passivation layer in areas 26 and 28 of the passivation layer 18. The removal of the photoresist may also not remove all photoresist that is in the keyhole 20 due to the narrow opening of the keyhole 20.
The strip of photoresist layer 22 includes a wet strip and a dry strip process. The wet strip applies in sequence Act 690, NMP, a DI rinse and a spin-dry step. The following dry strip is an O2 plasma strip at PSC. During this photoresist strip process, Act 690 and NMP will also flow into the keyhole and may, due to the narrow opening of the keyhole, not be easy to remove from the opening. After the completion of the above wet and dry strip processing steps (to remove the photoresist layer) there remains in the keyhole a mixture of left-over photoresist (photoresist that could not be reached due to the narrow entrance to the keyhole) with the Act 690 and NMP that entered the keyhole during the photoresist strip process.
Act 690 is a lift-off resist stripper and contains dimethyl sulfoxide and monoethanol-ammine.
NMP is a solvent-type stripper and contains N-Methyl-pyrolidinone.
A final alloy step is required for the curing of the passivation layer. This step takes place at temperatures up to 410 degrees C. During this alloy step the remnant Act 690 and NMP in the keyhole evaporates causing a violent chemical reaction resulting in the residue Act 690 and NMP to explode and extrude the remaining photoresist from the keyhole.
Prior Art can also use, within the above-indicated processing sequence, the deposition of a layer of SOG. FIG. 7 further highlights this approach. A interconnecting lines top layer metal pattern 12 with a bond pad top layer metal 14 for the bond pad is created as before, a passivation layer 16 of 2000 Angstrom of PE oxide is deposited over the metal pattern and the exposed surface of the substrate. Next a 3150-Angstrom thick layer 30 of SOG 314 is spin-coated; the objective of this layer is to enhance planarization of the keyholes and thereby to solve the above-indicated effects of passivation layer damage and photoresist extrusion from the keyhole. Over the layer 30 of SOG 314 a 7000-Angstrom thick layer 32 of PE Si3N4 is deposited and the process continues as indicated above, FIGS. 4 through 6. That is a layer 34 of photoresist is spin-coated, this layer is patterned (35) for the bonding pad 14, the layer 32 of PE Si3N4 is removed (33) above the bonding pad 12, the passivation layer 16 is removed (17) above the bond pad 14, the photoresist (34) is removed and a final alloy step is applied to the remainder of layer 32 of PE Si3N4.
The disadvantage of this approach is the additional cost of the SOG material and the required additional processing steps of SOG coating and SOG curing. Furthermore, SOG has the tendency to delaminate during subsequent packaging under high stress, which is highly detrimental to overall device reliability.
U.S. Pat. No. 4,733,289 (Tsurumaru) shows a resin-molded device using polyimide and nitride for passivation.
U.S. Pat. No. 5,242,864(Fassberg et al.) shows a polyimide protection layer.
U.S. Pat. No. 5,013,689(Yamamoto) shows a light sensitive polyimide layer used a passivation layer.
U.S. Pat. No. 5,091,289(Cronin et al.) shows a photosensitive polyimide composition.
U.S. Pat. No. 5,187,119(Cech et al.) shows a photosensitive polyimide and planarization process.
U.S. Pat. No. 5,807,787(Fu et al.) discloses a polyimide Passivation.
A principle objective of the present invention is to eliminate the negative effect that passivation layer imperfections have on device reliability.
Another objective of the present invention is to adapt planarization technology to ultra-small line spacing technologies.
Another objective of the present invention is to eliminate the effect of the formation of keyholes in dielectrics deposited within ultra-small line spacing.
Another objective of the present invention is to eliminate damage of cracking and delamination in the passivation layer caused by Spin-On-Glass technology.
Another objective of the present invention is to eliminate the Spin-On-Glass processing step.
Another objective of the present invention is to allow the deposition of thick and cross-link polyimide film thus preventing etching damage to the passivation layer.
Another objective of the present invention is to allow not having to remove the polyimide film from the wafer after etching thus further reducing the negative effect of keyhole extrusions.
The present invention teaches the creation of a pattern of top level metal for interconnecting lines and bond pads. A double layer of passivation is formed over the metal patterns, the present invention teaches the deposition of a thick layer of photosensitive polyimide over the passivation layers. This thick layer of photosensitive polyimide is patterned to expose the underlying bonding pads.
Key to the present invention is that the photosensitive polyimide is, after patterning for the bonding pad, not removed from the surface of the passivation layers. This thick layer of polyimide provides excellent protection of the passivation film that remains in place above the interconnecting lines. The polyimide further reduces stress during device packaging and it solves the problem of (the Prior Art) delamination of the SOG. The step of photoresist stripping has also been eliminated.